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september 2010 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 FAN6747 ? highly integrated green-mode pwm controller FAN6747 highly integrated green-mode pwm controller features ? high-voltage startup ? ac-line brownout protection by hv pin ? constant output power limit by hv pin (full ac-line range) ? built-in 8ms soft-start function ? two-level over-current protection (ocp) with 220ms debounce ? short-circuit protection (scp) with 15ms debounce as output short ? peak-current mode operation with cycle-by-cycle current limiting ? low startup current: 30a ? low operating current: 1.7ma ? over-temperature protection (otp) with an external negative-temperature-coefficient (ntc) thermistor ? pwm frequency decreasing at green-mode ? v dd over-voltage protection (ovp) ? internal latch circuit for ovp, otp, scp, and ocp applications general-purpose switch-mode power supplies and flyback power converters, including: ? power adapters ? smps with peak-current output, such as for printers, scanners, motor drivers ? ac/dc nb adapters ? open-frame smps description the highly integrated FAN6747 pwm controller provides several features to enhance the performance of flyback converters. to minimize standby power consumption, a proprietary green-mode function provides off-time modulation to decrease the switching frequency with load condition. under zero-load condition, the power supply enters burst mode and burst frequency can be low to save more power. green-mode function enables the power supply to meet international power conservation requirements. the FAN6747 is especially designed for smps with peak-current output. it incorporates a cycle-by-cycle current limiting and two-level over-current-protection (ocp) that can handle peak load with a debounce time. once the current is over the threshold level, it triggers the first counter 15ms and checks if v dd is below 10v; if it is, the pwm latches off for scp. if v dd is higher than 10v; it keeps counting to 220ms, then the pwm latches off for ocp. FAN6747 also integrates a frequency-hopping function internally to help reduce emi emission of a power supply with minimum line filters. built-in proprietary internal synchronized slope compensation achieves constant output power limit over universal ac line range. the gate output is clamped at 14v to protect the external mosfet from over-voltage damage. other protection functions include ac-line brownout protection with hysteresis and v dd over-voltage protection. for over-temperature protection, an external ntc thermistor can be applied to sense the ambient temperature. when ocp, ovp, scp, or otp is activated, an internal latch circuit latches off the controller. the latch is reset when the v dd supply is removed. ordering information part number operating temperature range package packing method FAN6747lmy -40 to +105c 8-lead, small-outline integrated circuit (soic), jedec ms-012, .15-inch narrow body tape & reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 2 FAN6747 ? highly integrated green-mode pwm controller application diagram figure 1. typical application internal block diagram gate fb sense gnd slope compensation vdd rt 5 5v soft driver s q r 1.05v 17v/10v uvlo green mode osc 1r blanking circuit ocp ovp delay scp delay debounce v dd-ovp v limit adjustment 0.7v 7 4 3 8 2 6 debounce1 debounce2 4.6v nc hv line voltage sample circuit brownout protection otp scp ocp latch protection ovp otp ocp scp v dd-scp 3r olp comparator ocp comparator current limit comparator pwm comparator internal bias soft-start circuit i rt hv startup auto restart protection figure 2. functional block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 3 FAN6747 ? highly integrated green-mode pwm controller marking information zxytt 6747f tpm figure 3. top mark pin configuration figure 4. pin assignments pin definitions pin # name description 1 gnd ground . this pin is used for the ground potential of all the pins. a 0.1f decoupling capacitor placed between vdd and gnd is recommended. 2 fb feedback . the output voltage feedback information from the external compensation circuit is fed into this pin. the pwm duty cycle is determined from this pin and the current-sense signal from pin 6. 3 nc no connection . 4 hv high-voltage startup . this pin is connected to the line input via diodes and resistors to achieve brownout and high/low line compensation. once the voltage of the hv pin is lower than the brownout voltage, pwm output is turned off. high/low line compensation dominates the ocp level and cycle-by-cycle current limit, to solves the unequal ocp level and power limit problem under universal input. 5 rt over-temperature protection . for over-temperature protection, an external ntc thermistor is connected from this pin to gnd. the impedance of the ntc decreases at high temperatures. once the voltage of the rt pin drops below the threshold voltage, the controller latches off the pwm. if the rt pin is not connected to the ntc resistor for over temperature protection, it is recommended to connect one 100k resistor to ground to prevent noise interference. this pin is limited by internal clamping circuit. 6 sense current sense . this pin is used to sense the mosfet current for the current mode pwm and ocp. if the switching current is higher than ocp threshold and lasts 220ms, the controller latches off the pwm. 7 vdd supply voltage . ic operating current and mosfet driving current are supplied using this pin. this pin is connected to an external bulk capacitor of typically 10f. the threshold voltages for startup and turn-off are 16.5v and 9v, respectively. the operating current is lower than 2ma. 8 gate gate driver output . the totem-pole output driver for the power mosfet. it is internally clamped below 14v. : fairchild logo z: plant code x: year code y: week code tt: die run code f: l = ocp latch t : package type (n =dip, m = sop) p: y = green compound m: manufacturing flow code
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 4 FAN6747 ? highly integrated green-mode pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage 30 v v hv suddenly input voltage to hv pin within 1 second (series connect with r hv ) 640 v v l input voltage to fb, sense, rt pin -0.3 7.0 v p d power dissipation (t a <50c) 400 mw ja thermal resistance (junction-to-ambient) 150 c/w t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature (soldering, 10 seconds) +260 c esd electrostatic discharge capability, all pins except hv pin human body model, jesd22-a114 4.50 kv charge device model, jesd22-c101 1.5 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltages, ar e given with respect to the network ground terminal. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit t a operating ambient temperature -40 +105 c v hv input voltage to hv pin 500 v r hv hv startup resistor 150 200 250 k ?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 5 FAN6747 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25c, unless otherwise specified. symbol parameter conditions min. typ. max. units vdd section v op continuously operating voltage 24 v v dd-on turn-on threshold voltage 15.5 16.5 17.5 v v dd-off pwm turn-off threshold voltage 8 9 10 v v dd-olp threshold voltage on v dd for hv jfet turn-on in protection condition after trigger ocp/ scp/ ovp/ otp 5.5 6.5 7.5 v v dd-lh threshold voltage on vdd pin for latch-off release voltage 3.5 4.0 4.5 v v dd-ac threshold voltage on vdd pin for disable ac recovery to avoid startup failed v dd-off +2.5 v dd-off +3.0 v dd-off +3.5 v v dd-scp threshold voltage on vdd pin for short-circuit protection (scp) v fb > v fbo v dd-off +0.5 v dd-off +1.0 v dd-off +1.5 v i lh holding current under latch-off conduction v dd =5v 80 100 120 a i dd-st startup current v dd-on ? 0.16v 30 a i dd-olp holding current at pwm-off phase v dd-olp +0.1v 210 270 330 a i dd-op1 operating supply current when pwm operating v dd =20v, v fb =3v gate open 1.7 2.0 ma i dd-op2 operating supply current when pwm stop v dd =20v, v fb =3v gate open 1.2 1.5 ma v dd-ovp threshold voltage on vdd pin for v dd over-voltage protection (latch-off) 24 25 26 v t d-ovp v dd ovp debounce time v fb > v fb-n 75 160 245 s figure 5. uvlo specification continued on following pages?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 6 FAN6747 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25c, unless otherwise specified. symbol parameter conditions min. typ. max. units figure 6. normal uvlo and two-step uvlo behavio r hv section i hv supply current drawn from hv pin v hv =120v, v dd =0v 1.50 2.75 4.00 ma v in-off pwm turn-off threshold dc source series r=200k to hv pin 92 102 112 v v in-on pwm turn-on threshold dc source series r=200k to hv pin 104 114 124 v ? v in change in v in , v in-on - v in-off dc source series r=200k to hv pin 6 12 18 v t s-cycle line voltage sample cycle v fb > v fb-n 170 205 240 s v fb < v fb-g 450 615 780 t s-time line voltage sample period 20 s t d_vin-off pwm turn-off debounce time v fb > v fb-n 65 75 85 ms v fb < v fb-g 180 235 290 ms figure 7. brownout circuit
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 7 FAN6747 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25c, unless otherwise specified. symbol parameter conditions min. typ. max. units figure 8. brownout behavio r figure 9. v dd-ac and ac recover y oscillator section f osc normal pwm frequency center frequency (v fb >v fb-n ) 61 65 69 khz t jtr-1 jitter period 1 v fb > v fb - n 3.9 4.4 4.9 ms t jtr-3 jitter period 3 v fb =v fb - g 10.2 11.5 12.8 ms f osc-g green-mode minimum frequency 19 22 25 khz v fb-n fb threshold voltage for frequency reduction beginning pin, fb voltage (v fb =v fb-n ), f osc ? 5khz 2.6 2.8 3.0 v jitter range 3.7 4.2 4.7 khz v fb-g fb threshold voltage for turn- off jitter and frequency reduction destination pin, fb voltage (v fb =v fb-g ) 2.1 2.3 2.5 v jitter range 1.45 khz
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 8 FAN6747 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25c, unless otherwise specified. symbol parameter conditions min. typ. max. units v oz-on fb threshold voltage for zero- duty recovery 1.6 1.8 2.0 v v fb-zdc (v oz-off ) fb threshold voltage for zero- duty 1.5 1.7 1.9 v v oz-on -v oz-off fb voltage hysteresis for v oz-on to v oz-off 50 100 150 mv f dv frequency variation vs. v dd deviation v dd =12v to 22v 5 % f dt frequency variation vs. temperature deviation t a =-40 to 105c 5 % figure 10. pwm frequency figure 11. burst-mode diagram feedback input section a v input-voltage to current-sense attenuation v fb < v fb-g 1/4.5 1/4.0 1/3.5 v/v z fb input impedance 13.4 15.5 17.6 k v fbo fb pin open voltage 4.8 5.0 5.2 v v fb-olp fb open-loop protection threshold voltage 4.3 4.6 4.9 v t d-olp open-loop protection debounce 190 215 240 ms
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 9 FAN6747 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25c, unless otherwise specified. symbol parameter conditions min. typ. max. units current sense section t pd delay to output 65 200 ns t leb leading-edge blanking time 230 270 310 ns v limit-l current limit at low line (v ac-rms =86v) v dc =122v, series r=200k to hv 0.790 0.825 0.860 v v limit-h current limit at high line (v ac-rms =259v) v dc =366v, series r=200k to hv 0.690 0.725 0.760 v v ocp-l ocp trigger level at low line (v ac-rms =86v) v dc =122v, series r=200k to hv 0.450 0.480 0.510 v v ocp-h ocp trigger level at high line (v ac =259v) v dc =366v, series r=200k to hv 0.390 0.420 0.450 v t soft-start period during startup startup time 7 8 9 ms t d-ocp debounce time for output ocp v cs >v ocp 190 215 240 ms t d-scp debounce time for output scp v cs >v ocp and v dd < v dd-scp 12 15 18 ms pwm output section dcy max maximum duty cycle 88.0 89.5 91.0 % v ol output voltage low v dd =15v, i o =50ma 1.5 v v oh output voltage high v dd =12v, i o =50ma 8 v t r rising time gate=1nf 95 ns t f falling time gate=1nf 30 ns v clamp gate output clamping voltage v dd =22v 11.0 13.5 16.0 v over-temperature protection section i rt output current of rt pin 92 100 108 a v otp-latch- off threshold voltage for over- temperature protection 1.00 1.05 1.10 v t d_otp-latch over-temperature latch-off debounce v fb > v fb-n 14 16 18 ms v fb < v fb-g 40 51 62 ms v otp2-latch- off second threshold voltage for over-temperature protection 0.65 0.70 0.75 v t d_otp2-latch second over-temperature latch-off debounce v fb > v fb-n 110 185 260 s v fb < v fb-g 320 605 890
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 10 FAN6747 ? highly integrated green-mode pwm controller typical performance characteristics 0 5 10 15 20 25 30 35 40 45 50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) i dd-st ( a) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) i dd-op1 (ma) figure 12. startup current (i dd-st ) vs. temperature figure 13. operation supply current (i dd-op1 ) vs. temperature 15 15.5 16 16.5 17 17.5 18 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v dd-on (v) 7.5 8 8.5 9 9.5 10 10.5 11 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v dd-off (v) figure 14. start threshold voltage (v dd-on ) vs. temperature figure 15. minimum operating voltage (v dd-off ) vs. temperature 0 2 4 6 8 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) i hv (ma) 1 2 3 4 5 6 7 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) i hv-lc (ua) figure 16. supply current drawn f rom hv pin (i hv ) vs. temperature figure 17. hv pin leakage current after startup (i h v -lc ) vs. temperature 59 60 61 62 63 64 65 66 67 68 69 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) f osc (khz) 88 88.5 89 89.5 90 90.5 91 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) dcy max (%) figure 18. frequency in no r mal mode ( f osc ) vs. temperature figure 19. maximum duty cycle (dc y max ) vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 11 FAN6747 ? highly integrated green-mode pwm controller typical performance characteristics 3 3.5 4 4.5 5 5.5 6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v fb-olp (v) 150 165 180 195 210 225 240 255 270 285 300 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) t d-olp (ms) figure 20. fb open-loop trigger level (v fb-olp ) vs. temperature figure 21. debounce time of fb pin open-loop protection (t d-olp ) vs. temperature 23 24 25 26 27 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v dd-ovp (v) 70 75 80 85 90 95 100 105 110 115 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) i rt ( a) figure 22. v dd over-voltage protection (v dd-ovp ) vs. temperature figure 23. output current from rt pin (i rt ) vs. temperature 0.8 0.9 1 1.1 1.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v otp (v) 0.5 0.6 0.7 0.8 0.9 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v otp2 (v) figure 24. over-temperature protection threshold voltage (v otp ) vs. temperature figure 25. over-temperature protection threshold voltage (v otp2 ) vs. temperature 104 106 108 110 112 114 116 118 120 122 124 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v in-on (v) 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v in-off (v) figure 26. brown-in (v in-on ) vs. temperature figure 27. brownout (v in-off ) vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 12 FAN6747 ? highly integrated green-mode pwm controller operation description startup current for startup, the hv pin is connected to the line input through an external diode and resistor, r hv , (1n4007 / 200k ? recommended). peak startup current drawn from the hv pin is (v ac 2 )/r hv and charges the hold-up capacitor through the diode and resistor. when the v dd capacitor level reaches v dd-on , the startup current switches off. at this moment, the v dd capacitor only supplies the FAN6747 to maintain the v dd before the auxiliary winding of the main transformer provides the operating current. operating current operating current is around 2ma. the low operating current enables better efficiency, power saving, and reduces the requirement of v dd hold-up capacitance. green-mode operation the proprietary green-mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. v fb , which is derived from the voltage feedback loop, is taken as the reference. once v fb is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22khz. two-level over-current protection (ocp) the cycle-by-cycle current limiting shuts down the pwm immediately when the sense voltage is over the limited threshold voltage (0.825v at low line). additionally, when the sense voltage is higher than the ocp threshold (0.48v at low line), the internal counter counts for 220ms, then latches off pwm. when ocp occurs, pwm output is turned off and v dd begins decreasing. when v dd goes below the turn-off threshold (~9v), the controller is totally shut down. v dd continues to discharge below v dd-olp by i dd-olp. then v dd is charged up to the turn-on threshold voltage of 16.5v through the startup resistor. when v dd is charged to 16.5v, it cycles again. this phenomenon is called two-level uvlo. brownout and constant power limited hv pin unlike previous pwm controllers, FAN6747?s hv pin isn?t only used for startup; it can also detect the ac line voltage to perform brownout function and set the current limit level. through a fast diode and startup resistor to sample the ac line voltage, the peak value refreshes and stores in register at each sampling cycle. w hen internal update time is met, this peak value is used to for brownout and current-limit level judgment. equations 1 and 2 can be used to calculate out the level of brown-in or brownout converted to rms value. for power saving, FAN6747 enlarges the sampling cycle to lower the power loss from hv sampling at light-load condition. 2 / ) 6 . 1 6 . 1 9 . 0 ( ) ( + = ? hv on ac r rms v (1) 2 / ) 6 . 1 6 . 1 81 . 0 ( ) ( + = ? hv off ac r rms v (2) k is r of unit the ; hv short-circuit protection (scp) this protection is used to handle the huge output demand if the power supply output is suddenly shorted to ground. if v dd drops under 10v and the sensed voltage is higher than the limited threshold voltage, scp is triggered and pwm output is latched off. this latch condition is reset only if v dd is discharged under 4v or by unplugging ac power line. under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 16.5v and 9v, respectively. during startup, the hold-up capacitor must be charged to 16.5v through the startup resistor to enable the ic. the hold-up capacitor continues to supply v dd before the energy can be delivered from auxiliary winding of the main transformer. v dd must not drop below 9v during startup. this uvlo hysteresis window ensures that the hold-up capacitor is adequate to supply v dd during startup. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs on the sense-resistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. during this blanking period, the current-limit comparator is disabled and can not switch off the gate driver. gate output / soft driving the bicmos output stage is a fast totem-pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 13.5v zener diode to protect power mosfet transistors against undesirable gate over voltage. a soft driving waveform is implemented to minimize emi. v dd over-voltage protection (ovp) v dd over-voltage protection is built in to prevent damage due to abnormal conditions. if the v dd voltage is over the over-voltage protection voltage (v dd-ovp ) and lasts for t d-ovp , the pwm pulses are disabled until the v dd voltage drops below 4v, then restarts again. soft-start for many applications, it is necessary to minimize the inrush current at startup. the built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 13 FAN6747 ? highly integrated green-mode pwm controller built-in slope compensation the sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6747 inserts a synchronized, positive-going, ramp at every switching cycle. constant output power limit when the sense voltage across sense resistor r s reaches the threshold voltage, the output gate drive is turned off after a small delay, t pd . this delay introduces an additional current proportional to t pd ? v in / l p . since the delay is nearly constant regardless of the input voltage v in , higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. to compensate this variation for a wide ac input range, a power-limiter is controlled by hv pin to solve the unequal power-limit problem. the power limiter is fed to the inverting input of the ocp comparator. this results in a lower current limit at high-line input than at low-line input. over-temperature protection (otp) a ntc thermistor, r ntc , in series with a resistor, r a , is connected from the rt pin to gnd pin. a constant current i rt is output from this pin. the voltage of the rt pin can be expressed as v rt = i rt ? (r ntc + r a ), where i rt is 100a, the headroom of v rt is limited at around 5v by internal circuitry. as high ambient temperatures occur, r ntc is smaller, such that the v rt decreases. when v rt is less than 1.05v(v otp ) but over 0.7v, the pwm turns off after t d_otp-latch . the other threshold, v dd under 0.7v, is used for fast shut down of FAN6747 after a short time. if the rt pin is not connected to the ntc resistor for over temperature protection, it is recommended to connect one 100k resistor to ground to prevent noise interference. this pin is limited by internal clamping circuit. noise immunity noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. slope compensation helps alleviate this problem. good placement and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components near the FAN6747, and increasing the power mos gate resistance improve performance.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 FAN6747 ? highly integrated green-mode pwm controller physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 28. 8-lead, small outline integrated circuit (soic) package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6747 ? rev. 1.0.3 15 FAN6747 ? highly integrated green-mode pwm controller

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